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英特尔10nm多次跳票 和摩尔定律终结

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lemoncap 发表于 2018-8-9 05:32 | 显示全部楼层 |阅读模式

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目前对于Intel的处理器产品来说,最大问题并不是AMD锐龙在后边一路追赶,而是自家的10nm工艺跳票几年了就是无法实现稳定量产。无论对于Intel自己,还是代工客户,这都是个大麻烦,最新消息称Intel将会缩减代工业务。
  其实,Intel的制程工艺在历史上几乎从来都是只考虑自家业务需要,对外代工比例很低,这不同于台积电、GlobalFoundries等纯代工型企业,也不同于三星这种兼顾自己和代工的。

                               
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  前几年,Intel也一直在努力扩大代工业务,尤其是14nm工艺节点相当开放,去年底还联合ARM宣布了10nm代工合作,包括10nm HPM、10nm HPM+、10nm HPM++三种版本,ARM处理器频率可达3.5GHz,而电压低至0.5V。
  不过,Intel的代工业务一直没能做大,尤其是10nm一直跳票,传闻说把一个全力押注Intel 10nm的大客户坑得都要破产了……
  从目前的情况看,Intel 10nm进入规模量产得明年下半年,而台积电已经开始量产7nm,三星的也快了,5nm都在全速推进。
  虽然说大家的工艺水平不能完全看数字,但就算台积电、三星的7nm等同于Intel 10nm,人家也是量产了,高通、华为、苹果都是大客户。
  曾有消息说Intel打算用其10nm争取华为麒麟的新订单,但显然没戏了。
  根据最新报道,Intel目前最大的代工客户是LG电子、展讯,比如展讯之前发布的SC9853I就是用了Intel 14nm工艺和x86架构。
  Altera曾是Intel最大代工客户,32nm工艺一路走到14nm工艺,不过已经被Intel收购。
  报道还称,由于新工艺推迟,难以争取到更多订单,Intel正在考虑缩减代工业务。




 楼主| lemoncap 发表于 2018-8-9 05:39 | 显示全部楼层
事实是英特尔10nm 最早也要明年底才能上市,跳票超过6年!

Intel Tick-Tock Roadmap
Cycle        Process        Introduction        Micro-archi-tecture
Tick        65 nm        2005        Pentium D
Tock        65 nm        2006        Core
Tick        45 nm        2007        Penryn
Tock        45 nm        2008        Nehalem
Tick        32 nm        2009        Westmere
Tock        32 nm        2010        Sandy Bridge
Tick        22 nm        2011        Ivy Bridge
Tock        22 nm        2013        Haswell
Tick        14 nm        2014        Broadwell
Tock        14 nm        2015        Skylake

最初的摩尔定律是3年线宽降低到一半
3431 发表于 2018-8-9 11:43 来自航空航天港手机版! | 显示全部楼层
lemoncap 发表于 2018-8-9 05:39
事实是英特尔10nm 最早也要明年底才能上市,跳票超过6年!

Intel Tick-Tock Roadmap

这意思是柠檬榨干了?
 楼主| lemoncap 发表于 2018-8-9 12:14 | 显示全部楼层
3431 发表于 2018-8-9 11:43
这意思是柠檬榨干了?

EUV光刻的科技树爬错了
 楼主| lemoncap 发表于 2018-8-9 12:17 | 显示全部楼层
EUV litho headed for failure, say SPIE keynoters
Mark LaPedus
3/1/2005 07:00 AM EST
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SAN JOSE, Calif. — Extreme ultraviolet (EUV) lithography is headed for failure despite Intel Corp.'s efforts to fund and push the technology into production fabs, according to keynote speakers at the SPIE Microlithography conference here on Monday (Feb. 28).

Lack of suitable power sources, photoresist issues and overall costs will continue to hamper EUV, a next-generation lithography (NGL) technology that is aimed for the 32-nm node in the 2009 time frame, according to experts at the SPIE event. EUV tool costs are estimated to be a staggering $40-to-$50 million per unit.

Still, Intel is pouring billions of dollars into the development of EUV. ASML Holding NV, Canon Inc., and Nikon Corp. are also separately developing EUV tools. In fact, ASML and Nikon on Tuesday (March 1) are expected to discuss the progress with their respective EUV programs at SPIE. Nikon claims to have printed 50-nm lines and spaces with its EUV tool, it was noted.

Some, however, doubt that EUV will ever see the light of day in the long run. "Unfortunately, it's not going to work," said Grant Willson, a co-founder of Molecular Imprints Inc. (MII) and professor of chemical engineering and chemistry at the University of Texas at Austin.

"No one will ever print a wafer for profit with EUV," Willson said in a keynote address at SPIE.

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MII (Austin, Texas) is developing nano-imprint lithography, which is a possible NGL candidate for the 32-nm node. Not surprisingly, Willson believes that nano-imprint will succeed — not EUV — in the long term.

Like EUV, nano-imprint also has its share of issues and remains untested. But lack of power sources remains a major problem for EUV. And at a recent EUV event in Japan, lithographers disclosed a new problem. EUV images below 40-nm with chemically amplified resists are unacceptable (see Nov. 19, 2004 story).

"I see no reason for (EUV)," said R. Fabian Pease, a professor of electrical engineering at Stanford University. "It's an example of a wolf in sheep's clothing," Pease said during a separate keynote at SPIE.

He was referring to EUV, a "soft X-ray" technology that performs in the 13-nm wavelength realm. It's a cousin of traditional X-ray lithography, which was abandoned after the industry spent billions of dollars to develop the technology in the 1970s and 1980s.

In fact, the semiconductor industry has attempted to develop some 50-to-70 different types of lithography technologies over the years, but only a "handful" of technologies have actually emerged in IC production fabs, namely optical, he said.

"It grieves me to say that optical is the choice for the foreseeable future," he lamented.

Pease himself has been involved in the development of electron-beam lithography and related techniques, which have also failed to succeed in today's high-volume production fabs.

Others disagreed with both Wilson and Pease. "I think (EUV) has tremendous promise," said Christopher Ober, a professor at Cornell University, during a keynote address, which centered around new and radical molecular resists for IC production.

Shinji Okazaki, director of EUV process technology research at the Association of Super-Advanced Electronics Technologies (ASET), an R&D organization based in Tokyo, said that EUV is suited for 45-nm half-pitch designs in production fabs.

At SPIE, ASML of the Netherlands is expected to give a progress report on its EUV project, which has been in the works for several years. ASML is expected to ship an alpha tool to IMEC by year's end.

Rival Nikon has devised a small-field EUV tool with a high-numerical- aperture of 0.3. Three sets of projection optics have been developed, with wave-front error rates of 7.5-, 1.9- and 0.9-nm.

The company claims that 50-nm lines and spaces were delineated with the tool. First shipments of the tool are due in 2006.
3431 发表于 2018-8-9 19:24 | 显示全部楼层
lemoncap 发表于 2018-8-9 12:17
EUV litho headed for failure, say SPIE keynoters
Mark LaPedus
3/1/2005 07:00 AM EST

不都用的是紫外光刻吗?有什么区别?
topzdx 发表于 2018-8-10 16:54 | 显示全部楼层
NUC  8I3CYSM2的英特尔“CrimsonCanyon” 有消息说是10nm的,但是从功耗上一点也看不出有改进......
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9m96e2 发表于 2018-8-10 17:01 | 显示全部楼层
lemoncap 发表于 2018-8-9 12:14
EUV光刻的科技树爬错了

跟EUV有个球关系,intel 10nm用的是DUV+SAQP,其他代工厂的7nm基本都是先DUV+LELELE,后期上EUV;TSMC的7nm下个月就要开始大规模上市了,GF和三星也就晚一个季度多点;无论是从特征尺寸,密度还是性能都是和intel 10nm同级,说到底跳票是intel自己的问题,很可能跟盲目追求密度有关

还有虽然说理论上EUV单次曝光性能不如DUV+SAQP而且成本可能更高,但几家趋之若鹜在7nm节点上EUV我觉得已经能说明一点问题了
 楼主| lemoncap 发表于 2018-8-11 05:10 | 显示全部楼层
topzdx 发表于 2018-8-10 16:54
NUC  8I3CYSM2的英特尔“CrimsonCanyon” 有消息说是10nm的,但是从功耗上一点也看不出有改进......

最新情况是延迟到2020年,至少XEON
 楼主| lemoncap 发表于 2018-8-11 05:11 | 显示全部楼层
topzdx 发表于 2018-8-10 16:54
NUC  8I3CYSM2的英特尔“CrimsonCanyon” 有消息说是10nm的,但是从功耗上一点也看不出有改进......

最新情况是延迟到2020年,至少XEON是
 楼主| lemoncap 发表于 2018-8-11 05:12 | 显示全部楼层
3431 发表于 2018-8-9 19:24
不都用的是紫外光刻吗?有什么区别?

真空紫外和普通紫外不一样
 楼主| lemoncap 发表于 2018-8-11 05:28 | 显示全部楼层
9m96e2 发表于 2018-8-10 17:01
跟EUV有个球关系,intel 10nm用的是DUV+SAQP,其他代工厂的7nm基本都是先DUV+LELELE,后期上EUV;TSMC的7 ...

这位小同志生怕我不懂DUV? 事情是这样的:
2005左右,英特尔就押宝EUV(见5楼),(我说NM你英特尔为嘛不信电子束嘛?)包括入股ASML。10多年了,EUV量产还是空中楼阁,193nm的DUV刻10nm~60nm那肯定是物理原理所不喜欢的,不管你多少多次掩膜、NA浸没、还有其它花招。 所以再往下DUV肯定是没多少潜力了。13.5nm的EUV (真空紫外)见所有的物质都大量产生光电子,和被强烈吸收,不管那是光刻胶、还是二氧化硅。所以EUV也不行。这就是EUV到现在拖了十多年还不能量产的根本原因。也是为何英特尔10nm拖延这么久的根本原因。
英特尔现在窝火于DUV不过就是EUV不能担当大任而已嘛? 不过事实证明了,这么多年英特尔还是14nm嘛。

现在半导体界缺少物理大师指导,所以缺少突破,资金大都都花在无用功上去了
 楼主| lemoncap 发表于 2018-8-11 05:33 | 显示全部楼层
Intel cuts stake in ASML to below 5 percent
DECEMBER 1, 2017 / 2:06 AM / 8 MONTHS AGO

AMSTERDAM (Reuters) - Chipmaker Intel (INTC.O) has cut its stake in Dutch semiconductor equipment supplier ASML (ASML.AS) to 4.96 percent, according to a filing published by the Dutch Financial Markets Authority on Friday.



Intel took a 15 percent stake in ASML in 2012 as part of a program to help the company invest in new technology needed to build the next generation of smaller, faster chips. With ASML’s new machines now beginning to enter commercial production, that investment program is winding down.

Intel Follows Samsung, Slashes Stake in ASML

ByEd Lin Sept. 15, 2017 8:01 a.m. ET


================================================================
为啥三星英特尔台积电最近半年多都减持 ASML? EUV不行嘛!



9m96e2 发表于 2018-8-11 10:13 来自航空航天港手机版! | 显示全部楼层
lemoncap 发表于 2018-8-11 05:28
这位小同志生怕我不懂DUV? 事情是这样的:
2005左右,英特尔就押宝EUV(见5楼),(我说NM你英特尔为嘛 ...

那可真是抱歉,现在学界的观点是DUV到intel标准的5-6nm毫无问题,其他三家用原始而成熟的光刻掩膜法都在量产7nm的边上了,5nm甚至更低的DUV方案也都有在准备

显然intel的问题在于心气太高, 既要1亿每平方毫米的密度又要维持甚至超过之前的性能
9m96e2 发表于 2018-8-11 10:18 来自航空航天港手机版! | 显示全部楼层
lemoncap 发表于 2018-8-11 05:28
这位小同志生怕我不懂DUV? 事情是这样的:
2005左右,英特尔就押宝EUV(见5楼),(我说NM你英特尔为嘛 ...

还有电子束曝光的速度问题怎么解决?二次散射问题也不见得是好解决的哦
 楼主| lemoncap 发表于 2018-8-12 01:49 | 显示全部楼层
9m96e2 发表于 2018-8-11 10:13
那可真是抱歉,现在学界的观点是DUV到intel标准的5-6nm毫无问题,其他三家用原始而成熟的光刻掩膜法都在 ...

注意,那不是真正的7nm, 而是7nm-Node, 即7纳米-节点, 里面的最小特征线宽cpp(大致等效于多晶硅栅级宽度,或栅级宽度的2倍)还是 50~60纳米的大小,只是因为有多层金属布线,或FIN三极管等的进展,现在可以用40~60纳米的最小线宽做原来(80年代)的~(大致)两层铝布线多晶栅标准6管SRAM需要7纳米设计规则(7纳米lambda,栅长14纳米)才能做到的密度。这就是英特尔始作俑者的xx纳米-节点的由来。就其初衷是为了粉饰摩尔定律的太平以保持其股市的吸引力。但是现在故事讲不下去了。英特尔是节点的始作俑者,后来台积电、三星知道后,好嘛,老子也吹,你吹14,我吹10,7,5,根本不考虑频率等特性。你说你革命,老子比你更革命,哈哈哈。 你说DUV行,老子说EUV更行,实际不行了回来说DUV还行,三星、台积电买了7、8亿的EUV,不都还耽搁在那里耶? 当了ASML的凯子而已。 所以前段,台积电某某某的啥5纳米、3纳米,当成抬举股价的宣传好不? 哄谁呢?


                               
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所以,你也不要说啥学界公认,很多人人云亦云,根本不知道自己在谈啥。
 楼主| lemoncap 发表于 2018-8-12 02:05 | 显示全部楼层
9m96e2 发表于 2018-8-11 10:18
还有电子束曝光的速度问题怎么解决?二次散射问题也不见得是好解决的哦

日立1998年就做出了高速直写电子束曝光机,每小时40片左右。直写二次电子问题不大,还可以降低电压,实在不行改用离子束
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9m96e2 发表于 2018-8-13 18:31 来自航空航天港手机版! | 显示全部楼层
lemoncap 发表于 2018-8-12 01:49
注意,那不是真正的7nm, 而是7nm-Node, 即7纳米-节点, 里面的最小特征线宽cpp(大致等效于多晶硅栅级宽 ...

废话,虚标节点这种稍对电子产品有了解的人都知道的常识还需要提及么?

可惜这里的5nm可是按照ITRS中的标准,实打实的5nm呢;SAQP在193nm DUV下可以做到19nm的最小间距,刚好是intel 10nm节点的一半。其他厂家等效10nm node的7nm工艺使用理论最大宽度比SAQP高出33%,实际曝光精度还要差不少的三次蚀刻,也从侧面说明DUV 完全是可以征服20nm间距的5nm节点的
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