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英特尔10nm多次跳票 和摩尔定律终结

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9m96e2 发表于 2018-8-13 18:54 来自航空航天港手机版! | 显示全部楼层
lemoncap 发表于 2018-8-12 02:05
日立1998年就做出了高速直写电子束曝光机,每小时40片左右。直写二次电子问题不大,还可以降低电压,实在 ...

Hitachi 那篇介绍HL-900D的paper很明确写了 “and a throughput of 1-3 wafers per
hour”,而且这是20cm晶圆的产量,不知道这个40片每小时是怎么来的呢?
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pbs 发表于 2018-8-30 03:36 | 显示全部楼层
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 楼主| lemoncap 发表于 2018-9-2 15:18 | 显示全部楼层
9m96e2 发表于 2018-8-13 18:54
Hitachi 那篇介绍HL-900D的paper很明确写了 “and a throughput of 1-3 wafers per
hour”,而且这是20c ...

那文章说的是:“Efforts are underway to achieve a throughput of 1-3 wafers at a time in the development of system ICs. ”“cm (8-in.) wafers and a throughput of 1-3 wafers perhour when deciding whether to cut over to opticallithography for the production phase or not.”


看附图咋说的? 20片每小时是不是? 这其实还是90年代中期的水平。 日立评论1995年到2000年有好多类似的文章,不过不少现在没有上线。
我记得有几期说的是对于某些ULSI是40WPH。
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 楼主| lemoncap 发表于 2018-9-2 15:34 | 显示全部楼层
pbs 发表于 2018-8-13 05:55
这太正常了,不这么干算不正常。英腿不可能浪费自己的领先优势。在amd 14纳米产品
尚未深入市场的情况下, ...


                               
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Intel 14nm的晶体管密度43.5百万/mm2   
台积电7nmFF的晶体管密度96.5百万/mm2
自己学会数数
 楼主| lemoncap 发表于 2018-9-2 15:44 | 显示全部楼层

这有求求的用?英特尔的10纳米 要2019年底才可能见到,如果不跳票的话。在这之前都是英特尔10纳米都是废话和Vaporware
 楼主| lemoncap 发表于 2018-9-2 15:47 | 显示全部楼层
GF放弃7nm及后续制程研发:尖端工艺太烧钱,不如继续沉迷14nm
雷锋网 企鹅号
2018-08-29 10:51:00
GF(GlobalFoundries,格罗方德),此前曾是AMD自家的半导体工厂,后由于AMD资金问题而拆分独立,被中东土豪穆巴达拉投资公司收入囊中。一直以来,GF、三星和台积电都是晶圆代工厂中拥有尖端工艺的三驾马车,雷锋网此前详细解读7nm制程的文章中,也曾介绍过GF在7nm制程节点的部署情况。

然而就在三星和台积电的7nm工艺以临阵待发时,GF突然决定退群不玩了。

雷锋网消息,GF昨天公布了一项重要的战略转变,决定停止在7nm工艺技术的所有工作及后续制程的研发,与AMD和IBM重新谈判其WSA和IP相关交易,并裁员5%。今后GF将专注于为新兴高增长市场的客户提供专业的制造工艺,包括射频芯片和嵌入式存储芯片等低功耗领域。

GF的CTO Gary Patton称,GF本有望在今年第四季度使用7nm工艺生产出客户的首批芯片,但“几周前”公司决定实施激烈的战略转变。他强调,做出该决定并非是GF遇到了重大技术问题,而是对其7nm平台以及财务问题的商业考虑。
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说明啥: 目前的光刻不管是DUV还是EUV的确都很难突破了
 楼主| lemoncap 发表于 2018-9-2 16:39 | 显示全部楼层
9m96e2 发表于 2018-8-13 18:31
废话,虚标节点这种稍对电子产品有了解的人都知道的常识还需要提及么?

可惜这里的5nm可是按照ITRS中 ...

Intel 10nm Yield Issues
by Scotten Jones
Published on 04-29-2018 02:00 PM 19 Comments  Comments

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EDA Consortium, Q3 2012 Revenue Numbers-intel-q1-2018.jpgOn their first quarter earnings call Intel announced that volume production of 10nm has been moved from the second half of 2018 to 2019 due to yield issues. Specifically, they are shipping 10nm in low volume now, but yield improvement has been slower than anticipated. They report that they understand the yield issues but that improvements will take time to implement and qualify.

During the question and answer segment they said it is "really tied to this being the last technology tied to not having EUV and the amount of multi patterning and the effects of that on defects".

This has led to a lot of speculation about what is causing the yield issues. I have seen some comments that everyone is doing multi-patterning Intel's explanation doesn't make sense and there is some speculation that the yield issues are related to cobalt. I thought it would be useful to explore multi-patterning usage and cobalt usage and how these differ between companies and what the impact may be on yields.

There are four companies currently pursuing leading edge logic: GLOBALFOUNDRIES (GF), Intel, Samsung, and TSMC. The following will explore multi-patterning and cobalt usage by company.

Multi-Patterning
In the front end of the line all four companies are using Self Aligned Quadruple Patterning (SAQP) with multiple cut masks for Fin formation and Self Aligned Double Patterning (SADP) for gate formation. At contact some versions of Litho-Etch are used, either Litho-Etch-Litho-Etch (LE2), or Litho-Etch-Litho-Etch-Litho-Etch (LE3) or even LE4 (EUV for Samsung). These are all similar between the companies except for Samsung's use of EUV. In the Back End Of Line (BEOL) is where we see a significant differences. GF and TSMC both use SADP for critical metal layers, Intel uses SAQP for 2 metal layers and Samsung is expected to use EUV for critical metal layers.

We believe GF and TSMC are both ramping yield on schedule. It is possible that the yield issues Intel is seeing are related to SAQP in the BEOL. BEOL metal layers require multiple block layers and this is complex to implement. The first block layer would remove the layers needed for subsequent block layers, the way this is addressed is block layers are applied as reverse images and then once all the block layers are done, the whole pattern is reversed. Implementing multiple block layers in concert with SAQP versus fewer block layers at SADP is more difficult. This could explain why multi-patterning may be more difficult at Intel. Intel has a 36nm pitch in the BEOL versus GF and TSMC at 40nm and the smaller pitch is more difficult to achieve. We don't know much about Samsung's process yield ramp or exact specifications but certainly their early use of EUV may presents some challenges for them and we wouldn't be surprised if Samsung encounters yield issues as well.

Cobalt Usage
I have also seen comments about cobalt usage suggesting Intel's use of cobalt may be the issue. The first comment I want to make here is everyone is using cobalt, not just Intel although there are differences in usage.

Liners/caps - we believe all four companies are using cobalt for liners and caps on critical metal layers. Historically liners are Ta/TaN and switching to Co/TaN improves electromigration and the copper "wetting" during processing. Cobalt caps on top of the metal lines also improve electromigration.
Contacts - we believe all four companies will also use cobalt filled contacts although there may be differences in how it is deposited (more on this later).
Local interconnect - Intel uses cobalt filled metal lines for M0 and M1, GF does not and we don't think TSMC does either. A key here is that as interconnect pitch shrinks, copper resistance goes up and eventually cobalt becomes a lower resistance solution. We believe Intel went to cobalt because it is beneficial for resistance at 36nm, with GF and TSMC at 40nm they likely didn't see the need. We are curious to see what happens with Samsung, we believe they may also have a 36nm minimum metal pitch and it will be interesting to see if they use cobalt interconnect. They are co-authors on technical papers for 7nm with cobalt M0 so they have certainly looked at it.


We know that GF uses CVD to deposit cobalt for their cobalt filled contact and we have heard that Intel deposits cobalt with plating. We have also heard that Intel may have void issues. Perhaps plating cobalt is creating some cobalt issues, we do not think there are fundamental issues with cobalt.

Conclusion
I believe Intel's comment on multi-patterning issues is probably the driver of their yield problems. They were more aggressive in their shrink than others and getting to 36nm minimum metal pitches with SAQP and multiple block layers is in my opinion the likely problem.
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开啥玩笑呢,36纳米的SAQP都良率上不去,还开啥玩笑20纳米SAQP。要控制侧向生长那么像PPT和动画那么容易? 不同面的沉积速度都不一样,一个表面张力;一个拐角就把你设计的形状破坏了,还不说腐蚀的选择性,各向异性等等。老夫90年代就气相沉积量子线等玩意,知道这里面水太深,绝大多数这种太FANCY的都失败。 历史上成功的自对准工艺都足够简单。
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pbs 发表于 2018-9-3 08:50 | 显示全部楼层
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pbs 发表于 2018-9-3 08:54 | 显示全部楼层
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9m96e2 发表于 2018-9-3 11:15 | 显示全部楼层
lemoncap 发表于 2018-9-2 15:18
那文章说的是:“Efforts are underway to achieve a throughput of 1-3 wafers at a time in the develo ...

问题在于这个实际生产的芯片不一定可以用这么低的复杂度啊
你后面这篇文章也是,SAQP的复杂度只是一个可能的假设啊,何况不是也可以把LE2和SADP结合起来用么?
ttx 发表于 2018-9-3 12:04 | 显示全部楼层
牙膏厂开始沦落到要和其他厂论战谁的制程更先进的地步了么?这是否也从侧面说明牙膏厂的制程神话开始破灭,被人家赶上来了,否则你看十年前哪个报道不是在吹牙膏厂先进制程抛离对手一代以上遥遥领先,那时候谁敢说自己制程领先英特尔?
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pbs 发表于 2018-9-4 02:09 | 显示全部楼层
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 楼主| lemoncap 发表于 2018-9-23 05:55 | 显示全部楼层
pbs 发表于 2018-9-3 08:50
英特尔10nm是1亿/mm2
台积电7nm是1亿不到/mm2

只是为了纠正你在18楼提到的:

Intel 14nm的晶体管密度比台积电7nm的还高。弯弯自己说的。”
 楼主| lemoncap 发表于 2018-9-23 06:22 | 显示全部楼层
9m96e2 发表于 2018-9-3 11:15
问题在于这个实际生产的芯片不一定可以用这么低的复杂度啊
你后面这篇文章也是,SAQP的复杂度只是一个可 ...

现在的多重pattern的FINFET的版图相对简单,这样逻辑和DRAM的复杂度差别不像20年前。20年前的DRAM能做到的,到现在扩展到CPU相对难度复杂度就没这么大了。同时当今CPU很大面积是L1-L3 cache, 或iGPU,图形相对简单, 接近于DRAM。 同时紫外光刻的多重pattern实际也大大降低了其throughput这个想象中的最大优势。综合看来e-beam 在当今,特别是多束电子束技术逐渐成熟的情况下,应该是代替紫外光刻的有效手段。
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 楼主| lemoncap 发表于 2018-9-23 06:31 | 显示全部楼层
ttx 发表于 2018-9-3 12:04
牙膏厂开始沦落到要和其他厂论战谁的制程更先进的地步了么?这是否也从侧面说明牙膏厂的制程神话开始破灭, ...

就是啊,英特尔不再是可望不可即
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